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?2006 silicon storage technology, inc. s71307-01-000 1/06 1 the sst logo and superflash are registered trademarks of silicon storage technology, inc. intel is a registered trademark of intel corporation. these specifications are subject to change without notice. preliminary specifications features: ? 4 mbit superflash memory array for code/data storage ? sst49lf004b: 512k x8 (4 mbit) ? conforms to intel lpc interface specification ? supports single-byte firmware memory cycle type ? flexible erase capability ? uniform 4 kbyte sectors ? uniform 64 kbyte overlay blocks ? chip-erase for pp mode only ? single 3.0-3.6v read and write operations ? superior reliability ? endurance: 100,000 cycles (typical) ? greater than 100 years data retention ? low power consumption ? active read current: 6 ma (typical) ? standby current: 10 a (typical) ? fast sector-erase/byte-program operation ? sector-erase time: 18 ms (typical) ? block-erase time: 18 ms (typical) ? chip-erase time: 70 ms (typical) ? byte-program time: 14 s (typical) ? chip rewrite time: 8 seconds (typical) ? single-pulse program or erase ? internal timing generation ? cmos and pci i/o compatibility ? two operational modes ? low pin count (lpc) interface mode for in-system operation ? parallel programming (pp) mode for fast production programming ?low pin count (l pc) interface mode ? lpc bus interface supporting byte read and write ? 33 mhz clock frequency operation ? wp# and tbl# pins provide hardware write protect for entire chip and/or top boot block ? block locking registers for individual block write-lock and lock-down protection ? jedec standard sdp command set ? data# polling and toggle bit for end-of-write detection ? 5 gpi pins for system design flexibility ? 4 id pins for multi-chip selection ? parallel programming (pp) mode ? 11-pin multiplexed address and 8-pin data i/o interface ? supports fast in-system or prom programming for manufacturing ? packages available ? 32-lead plcc ? 32-lead tsop (8mm x 14mm) ? all non-pb (lead-free) devices are rohs compliant product description the sst49lf004b flash memory devices are designed to interface with host controllers (chipsets) that support a low- pin-count (lpc) interface for bios applications. the sst49lf004b devices comply with intel?s lpc interface specification, supporting single-byte firmware memory cycle type. the sst49lf004b devices are backward compatible to the sst49lf004a firmware hub. in this document, fwh mode in the sst49lf004a specification is referenced as the firmware memory read/write cycle. two interface modes are supported by the sst49lf004b: lpc mode (firmware memory cycle types) for in-system operations and parallel programming (pp) mode to interface with pro- gramming equipment. the sst49lf004b flash memory devices are manufac- tured with sst?s proprietary, high-performance superflash technology. the split-gate cell design and thick-oxide tun- neling injector attain greater reliability and manufacturability compared with alternative approaches. the sst49lf004b devices significantly improve performance and reliability, while lowering power consumption. the sst49lf004b devices write (program or erase) with a single 3.0-3.6v power supply. the sst49lf004b use less energy during erase and pro- gram than alternative flash memory technologies. the total energy consumed is a function of the applied voltage, cur- rent and time of application. since for any given voltage range the superflash technology uses less current to pro- gram and has a shorter erase time, the total energy con- sumed during any erase or program operation is less than alternative flash memory technologies. the superflash technology provides fixed erase and pro- gram times, independent of the number of erase/program cycles that have occurred. this means the system software or hardware does not have to be calibrated or correlated to the cumulative number of erase cycles as is necessary with alternative flash memory technologies, whose erase and program times increase with accumulated erase/pro- gram cycles. 4 mbit firmware hub sst49lf004b sst49lf002b / 003b / 004b4mb firmware hub
2 preliminary specifications 4 mbit firmware hub sst49lf004b ?2006 silicon storage technology, inc. s71307-01-000 1/06 the sst49lf004b devices provide a maximum byte-pro- gram time of 20 sec. the entire memory can be erased and programmed byte-by-byte typically in 8 seconds for the sst49lf004b device, when using status detection fea- tures such as toggle bit or data# polling to indicate the completion of program operation. to protect against inad- vertent writes, the sst49lf004b device employ on-chip hardware and software data protection (sdp) schemes. it is offered with a typical endurance of 100,000 cycles. data retention is rated at greater than 100 years. to meet high density, surface mount requirements, the sst49lf004b is offered in both 32-lead plcc and 32- lead tsop packages. in addition, sst provides lead-free (non-pb) package options to address the growing need for non-pb solutions in electronic components. non-pb pack- age version can be obtained by ordering products with a package code suffix of ?e? as the environmental attribute in the product part number. see figures 1 and 2 for pin assignments and table 1 for pin descriptions. table of contents product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 list of tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 input/output communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 input communication frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 interface mode select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 identification inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 general purpose inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 write protect / top block lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 row / column select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 output enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 write enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 no connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 device memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 product identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
preliminary specifications 4 mbit firmware hub sst49lf004b 3 ?2006 silicon storage technology, inc. s71307-01-000 1/06 lpc mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 firmware memory read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 firmware memory write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 abort mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 response to invalid fields for firmware memory cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 multiple device selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 write operation status detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 parallel programming mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 write operation status detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 data protection (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 software command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 ac characteristics (lpc mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 ac characteristics (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 product ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 packaging diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4 preliminary specifications 4 mbit firmware hub sst49lf004b ?2006 silicon storage technology, inc. s71307-01-000 1/06 list of figures figure 1: pin assignments for 32-lead plcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2: pin assignments for 32-lead tsop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3: device memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4: firmware memory read cycle waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5: firmware memory write cycle waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 figure 6: lclk waveform (lpc mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 7: output timing parameters (lpc mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 8: input timing parameters (lpc mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 9: reset timing diagram (lpc mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 10: reset timing diagram (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 11: read cycle timing diagram (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 12: write cycle timing diagram (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 13: data# polling timing dia gram (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 14: toggle bit timing diagram (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 15: byte-program timing diagram (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 16: sector-erase timing diagram (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0 figure 17: block-erase timing diagram (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 18: chip-erase timing diagram (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 19: software id entry and read (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 20: software id exit (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 21: ac input/output reference waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 22: a test load example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
preliminary specifications 4 mbit firmware hub sst49lf004b 5 ?2006 silicon storage technology, inc. s71307-01-000 1/06 list of tables table 1: pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 2: product identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3: firmware memory cycles start field definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 4: firmware memory read cycle field definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 5: firmware memory write cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 6: firmware memory multiple device selection configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 7: block locking registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 8: block locking register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 9: operation modes selection (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 10: software command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 11: dc operating characteristics (all interfaces) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 12: recommended system power-up timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 13: pin capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 14: reliability characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 15: clock timing parameters (lpc mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 16: read/write cycle timing parameters (lpc mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 17: ac input/output specifications (lpc mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 table 18: interface measurement condition parameters (lpc mode) . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 19: reset timing parameters (lpc mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 20: reset timing parameters (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 21: read cycle timing parameters (pp mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 22: program/erase cycle timing parameters (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 23: revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6 preliminary specifications 4 mbit firmware hub sst49lf004b ?2006 silicon storage technology, inc. s71307-01-000 1/06 functional blocks 1307 b1.0 y-decoder i/o buffers and data latches address buffers & latches x-decoder superflash memory control logic lclk rst# mode gpi[4:0] programmer interface wp# tbl# init# id[3:0] lframe# r/c# oe# we# a[10:0] dq[7:0] lad[3:0] lpc interface f unctional b lock d iagram
preliminary specifications 4 mbit firmware hub sst49lf004b 7 ?2006 silicon storage technology, inc. s71307-01-000 1/06 pin assignments figure 1: p in a ssignments for 32- lead plcc figure 2: p in a ssignments for 32- lead tsop 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 a7(gpi1) a6 (gpi0) a5 (wp#) a4 (tbl#) a3 (id3) a2 (id2) a1 (id1) a0 (id0) dq0 (lad0) mode (mode) v ss (v ss ) nc nc v dd (v dd ) oe# (init#) we# (lframe#) nc dq7 (res) 4 3 2 1 32 31 30 a8 (gpi2) a9 (gpi3) rst# (rst#) nc v dd (v dd ) r/c# (lclk) a10 (gpi4) 32-lead plcc top view 1307 32-plcc p1.0 14 15 16 17 18 19 20 dq1 (lad1) dq2 (lad2) v ss (v ss ) dq3 (lad3) dq4 (res) dq5 (res) dq6 (res) ( ) designates lpc mode nc nc nc v ss (v ss ) mode (mode) a10 (fgpi4) r/c# (clk) v dd (v dd ) nc rst# (rst#) a9 (fgpi3) a8 (fgpi2) a7 (fgpi1) a6 (fgpi0) a5 (wp#) a4 (tbl#) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 oe# (init#) we# (lframe#) v dd (v dd ) dq7 (res) dq6 (res) dq5 (res) dq4 (res) dq3 (lad3) v ss (v ss ) dq2 (lad2) dq1 (lad1) dq0 (lad0) a0 (id0) a1 (id1) a2 (id2) a3 (id3) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1307 32-tsop wh p1.0 standard pinout top view die up ( ) designates lpc mode
8 preliminary specifications 4 mbit firmware hub sst49lf004b ?2006 silicon storage technology, inc. s71307-01-000 1/06 pin descriptions table 1: p in d escription symbol pin name type 1 1. i = input, o = output interface functions pp lpc lclk clock i x to provide a clock input to the control unit. the clock conforms to the pci specification. lad[3:0] address and data i/o x to provide lpc bus information such as addresses and command inputs/outputs to memory. lframe# frame i x to indicate start of a data transfer operat ion; also used to abort an lpc cycle in progress. mode interface mode select ixx this pin determines which interface is operational. when held high, programmer mode is enabled and when held low, lpc mode is enabled. this pin must be set at power-up or before returning from reset and must not change during device opera- tion. this pin must be held high (v ih ) for pp mode and low (v il ) for lpc mode. this pin is internally pulled-down with a resistor between 20-100 k . rst# reset i x x to reset the operation of the device init# initialize i x this is the second reset pin for in-system use. this pin functions id entically to rst#. id[3:0] identification inputs ix these four pins are part of the mechanism that allows multiple parts to be attached to the same bus. the strapping of these pi ns is used to identify the component. the boot device must have id[3:0]=0000, al l subsequent devices should use sequential count-up strapping. these pins are intern ally pulled-down with a resistor between 20-100 k . gpi[4:0] general purpose inputs ix these individual inputs can be used for additional board flexibility. the state of these pins can be read through gpi_reg (general purpose inputs register). these inputs should be at their desired state before the start of the lpc clock cycle during which the read is attempted, and should remain in place until the end of the read cycle. unused gpi pins must not be floated. tbl# top block lock i x when low, prevents programming to the boot block sectors at the top of the device memory. when tbl# is high it disables har dware write protection for the top block sectors. this pin cannot be left unconnected. wp# write protect i x when low, prevents programming to all but the highest addressable blocks. when wp# is high it disables hardware write prot ection for these blocks. this pin cannot be left unconnected. r/c# row/column select ix select for the programming interface, this pin determines whether the address pins are pointing to the row addresses, or to the column addresses. a 10 -a 0 address i x inputs for low-order addresses during re ad and write operations. addresses are internally latched during a write cycle. for the programming interface, these addresses are latched by r/c# and share the same pins as the high-order address inputs. dq 7 -dq 0 data i/o x to output data during read cycles and receive input data during write cycles. data is internally latched during a write cycle. the outputs are in tri-state when oe# is high. oe# output enable i x to gate the data output buffers. we# write enable i x to control the write operations. res reserved x these pins must be left unconnected. v dd power supply pwr x x to provide power supply (3.0-3.6v) v ss ground pwr x x circuit ground (0v reference) nc no connection n/a n/a unconnected pins. t1.2 1307
preliminary specifications 4 mbit firmware hub sst49lf004b 9 ?2006 silicon storage technology, inc. s71307-01-000 1/06 clock the lclk pin accepts a clock input from the host controller. input/output communications the lad[3:0] pins are used to serially communicate cycle information such as cycle type, cycle direction, id selection, address, data, and sync fields. input communication frame the lframe# pin is used to indicate start of a lpc bus cycle. the pin is also used to abort an lpc bus cycle in progress. interface mode select the mode pin is used to set the interface mode. if the mode pin is set to logic high, the device is in pp mode. if the mode pin is set low, the device is in the lpc mode. the mode selection pin must be configured prior to device oper- ation. the mode pin is internally pulled down if the pin is left unconnected. reset a v il on init# or rst# pin initiates a device reset. init# and rst# pins have the same function internally. it is required to drive init# or rst# pins low during a system reset to ensure proper cpu initialization. during a read operation, driving init# or rst# pins low deselects the device and places the output drivers, lad[3:0], in a high impedance state. the reset signal must be held low for a minimum of time t rstp . a reset latency occurs if a reset pro- cedure is performed during a program or erase operation. see tables 19 and 20, reset timing parameters, for more information. a device reset during an active program or erase operation will abort the operation and memory con- tents may become invalid due to data being altered or cor- rupted from an incomplete erase or program operation. identification inputs these pins are part of a mechanism that allows multiple devices to be attached to the same bus. the strapping of these pins is used to identify the component. the boot device must have id[3:0] = 0; all subsequent devices should use sequential count-up strapping. these pins are internally pulled-down with a resistor between 20-100 k . general purpose inputs the general purpose inputs (gpi[4:0]) can be used as dig- ital inputs for the cpu to read. the gpi register holds the values on these pins. the da ta on the gpi pins must be stable before the start of a gpi register read and remain stable until the read cycle is complete. the pins must be driven low, v il , or high, v ih but not left unconnected (float). write protect / top block lock the top boot lock (tbl#) and write protect (wp#) pins are provided for hardware write protection of device mem- ory in the sst49lf004b. the tbl# pin is used to write protect 16 boot sectors (64 kbyte) at the highest memory address range for the sst49lf004b. the wp# pin write protects the remaining sectors in the flash memory. an active low signal at the tbl# pin prevents program and erase operations of the top boot block. when tbl# pin is held high, the hardware write protection of the top boot block is disabled. the wp# pin serves the same function for the remaining blocks of the device memory. the tbl# and wp# pins write protection functions operate independently of one another. both tbl# and wp# pins must be set to their required protection states prior to starting a program or erase operation. a logic level change occurring at the tbl# or wp# pin during a program or erase operation could cause unpredictable results. row / column select the r/c# pin is used to control the multiplex address inputs in parallel programming (pp) mode. the column addresses are mapped to the higher internal address (a 18-11 ), and the row addresses are mapped to the lower internal addresses (a 10-0 ). output enable the oe# pin is used to gate the output data buffers in pp mode. write enable the we# pin is used to control the write operations in pp mode. no connection these pins are not connected internally.
10 preliminary specifications 4 mbit firmware hub sst49lf004b ?2006 silicon storage technology, inc. s71307-01-000 1/06 device memory map figure 3: d evice m emory m ap design considerations sst recommends a high frequency 0.1 f ceramic capac- itor to be placed as close as possible between v dd and v ss less than 1 cm away from the v dd pin of the device. additionally, a low frequency 4.7 f electrolytic capacitor from v dd to v ss should be placed within 1 cm of the v dd pin. if a socket is used for programming purposes, an addi- tional 1-10 f should be added next to each socket. the rst# and init# pins must remain stable at v ih for the entire duration of an erase or program operation. wp# must remain stable at v ih for the entire duration of the erase and program operations for non-boot block sectors. to write data to the top boot block sectors, the tbl# pin must also remain stable at v ih for the entire duration of the erase and program operations. product identification the product identification mode identifies the device as the sst49lf004b and manufacturer as sst. 7ffffh 70000h 6ffffh 60000h 5ffffh 50000h 4ffffh 40000h 3ffffh 30000h 2ffffh 20000h 1ffffh 10000h 0f000h 02000h 01000h 00000h boot block 4 kbyte sector 1 4 kbyte sector 2 4 kbyte sector 0 block 7 block 6 block 5 block 4 block 3 block 2 block 1 block 0 1307 f02.0 wp# block 0-6 tbl# (64 kbyte) table 2: p roduct i dentification address data pp mode lpc mode 1 1. address shown in this column is for boot device only. address locations should appear elsewhere in the 4 gbyte system memory map depending on id strapping values on id[3:0] pins when multiple lpc memory devices are used in a system. manufacturer?s id 0000h ffbc 0000h bfh device id 2 2. the device id for sst49lf004b is the same as sst49lf004a. sst49lf004b 0001h ffbc 0001h 60h t2.0 1307
preliminary specifications 4 mbit firmware hub sst49lf004b 11 ?2006 silicon storage technology, inc. s71307-01-000 1/06 mode selection the sst49lf004b flash memory device operates in two distinct interface modes: the lpc mode and the parallel programming (pp) mode. the mode (interface mode select) pin is used to set the interface mode selection. if the mode pin is set to logic high, the device is in pp mode; while if the mode pin is set low, the device is in lpc mode. the mode selection pin must be configured prior to device operation and must not change during operation. if the pin is not connected, by default the mode pin is internally pulled low and t he 49lf00xb will be in lpc operation. in lpc mode, communication between the host and the sst49lf004b occurs via the 4- bit i/o communication sig- nals, lad[3:0] and lframe#. the sst49lf004b detects whether it is being accessed via a fwh read or fwh write cycle by detecting the start field contents; 91101b is a fwh read cycle and a 1110b indicates a fwh write cycle. in pp mode, the device is controlled via the 11 addresses, a 10 -a 0 , and 8 i/o, dq 7 -dq 0 , signals. the address inputs are multiplexed in row and column selected by control sig- nal r/c# pin. the row addresses are mapped to the lower internal addresses (a 10-0 ), and the column addresses are mapped to the higher internal addresses (a 18-11 ). see fig- ure 3, device memory map, for address assignments. lpc mode device operation the lpc mode uses a 5-signal communication interface consisting of one control line, lframe#, which is driven by the host to start or abort a bus cycle, and a 4-bit data bus, lad[3:0], which is used to communicate cycle type, cycle direction, id selection, addres s, data and sync fields. the device enters standby mode when lframe# is high and no internal operation is in progress. the sst49lf004b supports single-byte firmware mem- ory read/write cycles as defi ned in intel?s low-pin-count interface specification. the host drives lframe# low for one or more clock cycles to initiate an lpc cycle. the last latched value of lad[3:0] before lframe# is the start value. the start value determines whether the sst49lf004b will respond to a firmware memory read or firmware memory write cycle as defined in table 3. see following sections for details of firmware memory cycle types. jedec standard sdp (software data protec- tion) program and erase command sequences are used to initiate firmware memory program and erase opera- tions. see table 9 for a listing of program and erase com- mands. chip-erase is only available in pp mode. table 3: f irmware m emory c ycles start f ield d efinition start value definition 1101 start of a firmware memory read cycle 1110 start of a firmware memory write cycle t3.0 1307
12 preliminary specifications 4 mbit firmware hub sst49lf004b ?2006 silicon storage technology, inc. s71307-01-000 1/06 firmware memory read cycle figure 4: f irmware m emory r ead c ycle w aveform table 4: f irmware m emory r ead c ycle f ield d efinitions clock cycle field name field contents lad[3:0] 1 1. field contents are valid on the ri sing edge of the present clock cycle. lad[3:0] direction comments 1 start 1101 in lframe# must be active (low) for the device to respond. only the last field latched before lframe# transitions high will be recognized. the start field contents (1101b) indi- cate a firmware memory read cycle. 2 idsel 0000 to 1111 in indicates which sst49lf004b device should respond. if the idsel (id select) field matches the value of id[3:0], the device will respond to the lpc bus cycle. 3-9 maddr yyyy in these seven clock cyc les make up the 28-bit memory address. yyyy is one nibble of the entire address. addresses are transferred most-significant nibble first. 10 msize 0000 (1 byte) in the msize field indicates how many bytes will be trans- ferred during multi-byte operations. the sst49lf004b only supports single-byte operation. msize=0000b 11 tar0 1111 in then float in this clock cycle, the master has driven the bus to all ?1?s and then floats the bus, prior to the next clock cycle. this is the first part of the bus ?turnaround cycle.? 12 tar1 1111 (float) float then out the sst49lf004b takes control of the bus during this cycle. 13 rsync 0000 (ready) out during this clock cycle, the device generates a ?ready sync? (rsync) indicating that the device has received the input data. 14 data zzzz out zzzz is the least-significant nibble of the data byte. 15 data zzzz out zzzz is the most-significant nibble of the data byte. 16 tar0 1111 out then float in this clock cycle, the sst49lf004b drives the bus to all ones and then floats the bus prior to the next clock cycle. this is the first part of the bus ?turnaround cycle.? 17 tar1 1111 (float) float then in the host resumes co ntrol of the bus during this cycle. t4.1 1307 1307 f03.0 lframe# lad[3:0] 1101b 0000b a[23:20] a[19:16] a[3:0] a[7:4] a[11:8] a[15:12] maddr start idsel msize lclk a[27:24] 0000b rsync ta r 1 ta r 0 ta r d[7:4] tri-state d[3:0] 0000b 1111b data
preliminary specifications 4 mbit firmware hub sst49lf004b 13 ?2006 silicon storage technology, inc. s71307-01-000 1/06 firmware memory write cycle figure 5: f irmware m emory w rite c ycle w aveform table 5: f irmware m emory w rite c ycle clock cycle field name field contents lad[3:0] 1 1. field contents are valid on the ri sing edge of the present clock cycle. lad[3:0] direction comments 1 start 1110 in lframe# must be active (low) for the device to respond. only the last field latched before lframe# transitions high will be recognized. the start field contents (1110b) indicate a firmware memory write cycle. 2 idsel 0000 to 1111 in indicates which sst49lf004b device should respond. if the idsel (id select) field matches the value of id[3:0], the device will respond to the mem- ory cycle. 3-9 maddr yyyy in these seven clock cycles make up the 28-bit memory address. yyyy is one nibble of the entire address. addresses are transferred most-significant nibble first. 10 msize 0000 (1 byte) in the msize field indicates how many bytes will be transferred during multi-byte operations. the device only supports single-byte writes. msize=0000b 11 data zzzz in zzzz is the least-sign ificant nibble of the data byte. 12 data zzzz in zzzz is the most-significant nibble of the data byte. 13 tar0 1111 in then float in this clock cycle, the host drives the bus to all '1's and then floats the bus prior to the next clock cycle. this is the first part of the bus ?turnaround cycle.? 14 tar1 1111 (float) float then out the sst49lf004b takes control of the bus during this cycle. 15 rsync 0000 out during this clock cycle, the device generates a ?ready sync? (rsync) indicating that the device has received the input data. 16 tar0 1111 out then float in this clock cycle, the sst49lf004b drives the bus to all '1's and then floats the bus prior to the next clock cycle. this is the first part of the bus ?turnaround cycle.? 17 tar1 1111 (float) float then in the host resumes control of the bus during this cycle. t5.0 1307 1307 f04.0 lframe# lad[3:0] 1110b 0000b a[23:20] a[19:16] a[3:0] a[7:4] a[11:8] a[15:12] maddr start idsel msize lclk a[27:24] 0000b rsync ta r 1 ta r 0 ta r data d[7:4] tri-state d[3:0] 0000b 1111b
14 preliminary specifications 4 mbit firmware hub sst49lf004b ?2006 silicon storage technology, inc. s71307-01-000 1/06 abort mechanism if lframe# is driven low for one or more clock cycles after the start of a bus cycle, the cycle will be terminated. the host may drive lad[3:0] with '1111b' (abort nibble) to return the interface to ready mode. the abort only affects the current bus cycle. for a multi-cycle command sequence, such as the erase or program sdp commands, abort doesn't interrupt the entire command sequence, only the current bus cycle of the command sequence. the host can re-send the bus cycle for the aborted command and continue the sdp command sequence after the device is ready again. response to invalid fi elds for firmware memory cycle during lpc operations the sst49lf004b will not explicitly indicate that it has received invalid field sequences. the response to specific invalid fields or sequences is as fol- lows: id mismatch: if the idsel field does not match id[3:0], the device will ignore the cycle. see multiple device selec- tion section for details. address out of range: the address sequence is 7 fields long (28 bits) for firmware memory bus cycles, but only a 22 and a 18 :a 0 will be decoded by sst49lf004b. address a 22 has the special function of directing reads and writes to the flash core (a 22 =1) or to the register space (a 22 =0). invalid msize field if the device receives an invalid msize field during a firmware memory read or write cycle, the cycle will be i gnored and no operation will be attempted. the sst49lf004b will not generate any kind of response in this situation. invalid size fields for a firm- ware memory cycle are any data other than 0000b. once valid start, idsel, and msize fields are received, the sst49lf004b will always complete the bus cycle. however, if the device is busy performing a flash erase or program operation, no new write command (memory write or register write) will be executed. multiple device selection multiple lpc flash devices may be strapped to increase memory densities in a system. the four id pins, id[3:0], allow up to 16 devices to be attached to the same bus by using different id strapping in a system. bios support, bus loading, or the attaching bridge may limit this number. the boot device must have an id of 0000b (determined by id[3:0]); subsequent devices use incremental numbering. equal density must be used with multiple devices. multiple device selection for firmware memory cycle for firmware memory read/write cycles, hardware strap- ping values on id[3:0] must match the values in idsel field. see table 6 for multiple device selection configura- tions. the sst49lf004b will co mpare the idsel field with id[3:0]'s strapping values. if there is a mismatch, the device will ignore the reminder of the cycle. table 6: f irmware m emory m ultiple d evice s election c onfiguration device # id[3:0] idsel 0 (boot device) 0000 0000 1 0001 0001 2 0010 0010 3 0011 0011 4 0100 0100 5 0101 0101 6 0110 0110 7 0111 0111 8 1000 1000 9 1001 1001 10 1010 1010 11 1011 1011 12 1100 1100 13 1101 1101 14 1110 1110 15 1111 1111 t6.0 1307
preliminary specifications 4 mbit firmware hub sst49lf004b 15 ?2006 silicon storage technology, inc. s71307-01-000 1/06 write operation status detection the sst49lf004b device provides two software means to detect the completion of a write (program or erase) cycle, in order to optimize the system write cycle time. the soft- ware detection includes two status bits: data# polling, dq 7, and toggle bit, dq 6. the end-of-write detection mode is incorporated into the firmware memory read cycles. the actual completion of the nonvolatile write is asynchronous with the system. therefore, either a data# polling or toggle bit read may be simultaneous with the completion of the write cycle. if this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either dq 7 or dq 6. in order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. if both reads are valid, then the device has completed the write cycle, otherwise the rejection is valid. data# polling when the sst49lf004b device is in the internal program operation, any attempt to read dq 7 will produce the com- plement of the true data. once the program operation is completed, dq 7 will produce true data. note that even though dq 7 may have valid data immediately following the completion of an internal write operation, the remaining data outputs may still be in valid. valid data will appear on the entire data bus in subs equent successive read cycles after an interval of 1 s. during an internal erase operation, any attempt to read dq 7 will produce a '0'. once the inter- nal erase operation is completed, dq 7 will produce a '1'. proper status will not be given using data# polling if the address is in the invalid range. toggle bit during the internal program or erase operation, any consec- utive attempts to read dq 6 will produce alternating 0s and 1s, i.e., toggling between 0 and 1. when the internal pro- gram or erase operation is completed, the toggling will stop. note that even though dq 6 may have valid data immediately following the completion of an internal write operation, the remaining data outputs may still be invalid. valid data will appear on the entire data bus in subsequent successive read cycles after an interval of 1 s. proper status will not be given using toggle bit if the address is in the invalid range. registers there are three types of registers available on the sst49lf004b, the general purpose inputs register, block locking registers, and the jedec id registers. these reg- isters appear at their respective address location in the 4 gbyte system memory map. unused register locations will read as 00h. any attempt to read or write any register dur- ing an internal write o peration will be ignored. general purpose inputs register the gpi_reg (general purpose inputs register) passes the state of gpi[4:0] to the outputs. it is recommended that the gpi[4:0] pins are in the desired state before lframe# is brought low for the beginning of the bus cycle, and remain in that state until the end of the cycle. there is no default value since this is a pass-through register. the gpi register for the boot device appears at ffbc0100h in the 4 gbyte system memory map, and will appear elsewhere if the device is not the boot device. the register is not available to be read when the device is in erase/program operation. block locking registers sst49lf004b provides software controlled lock protection through a set of block locking registers. the block locking registers are read/write registers and are accessible through standard addressable memory locations specified in table 7 for boot device. these registers will appear else- where if the device is not the boot device. unused register locations will read as 00h. write lock: the write-lock bit, bit 0, controls the lock state. the default write status of all blocks after power up is write locked. when bit 0 of the block locking register is set, program and erase operations for the corresponding block are prevented. clearing the writ e-lock bit will unprotect the block. the write-lock bit must be cleared prior to starting a program or erase operation since it is sampled at the beginning of the operation. the write-lock bit functions in conjunction with the hard- ware write lock pin tbl# for the top boot block. when tbl# is low, it overrides the software locking scheme. the top boot block locking register does not indicate the state of the tbl# pin. the write-lock bit functions in conjunction with the hard- ware wp# pin for blocks 0 to 6. when wp# is low, it over- rides the software locking scheme. the block locking registers do not indicate the state of the wp# pin.
16 preliminary specifications 4 mbit firmware hub sst49lf004b ?2006 silicon storage technology, inc. s71307-01-000 1/06 lock down: the lock-down bit, bit 1, controls the block locking registers. the default lock down status of all blocks upon power-up is not locked down. once the lock-down bit is set, any future attempted changes to that block locking register will be ignored. the lock- down bit is only cleared upon a device reset with rst# or init# or power down. current lock down status of a par- ticular block can be determined by reading the corre- sponding lock-down bit. once the lock-down bit of a block is set, the write-lock bits for that block can no longer be modified, and the block is locked down in its current state of write accessibility. jedec id registers the jedec id registers provide access to the manufac- turer and device id information with a single read cycle. the jedec id registers for the boot device appear at ffbc0000h and ffbc0001h in the 4 gbyte system memory map, and will appear el sewhere if the device is not the boot device. registers are not available for read when the device is in erase/program operation. unused register location will read as 00h. refer to table 2 for product identi- fication information. table 7: b lock l ocking r egisters 1 1. default value at power up is 01h register block size protected memory address range memory map register address t_block_lk 64k 07ffffh - 070000h ffbf0002h t_minus01_lk 64k 06ffffh - 060000h ffbe0002h t_minus02_lk 64k 05ffffh - 050000h ffbd0002h t_minus03_lk 64k 04ffffh - 040000h ffbc0002h t_minus04_lk 64k 03ffffh - 030000h ffbb0002h t_minus05_lk 64k 02ffffh - 020000h ffba0002h t_minus06_lk 64k 01ffffh - 010000h ffb90002h t_minus07_lk 64k 00ffffh - 000000h ffb80002h t7.0 1307 table 8: b lock l ocking r egister b its reserved bit [7..2] lock-down bit [1] write-lock bit [0] lock status 000000 0 0 full access 000000 0 1 write locked (default state at power-up) 000000 1 0 locked open (full access locked down) 000000 1 1 write locked down t8.0 1307
preliminary specifications 4 mbit firmware hub sst49lf004b 17 ?2006 silicon storage technology, inc. s71307-01-000 1/06 parallel programming mode device operation commands are used to initiate the memory operation func- tions of the device. the data portion of the software com- mand sequence is latched on the rising edge of we#. during the software command sequence the row address is latched on the falling edge of r/c# and the column address is latched on the rising edge of r/c#. read the read operation of the sst49lf004b device is con- trolled by oe#. oe# is the output control and is used to gate data from the output pins. refer to the read cycle tim- ing diagram, figure 11, for further details. reset a v il on rst# pin initiates a device reset. byte-program operation the sst49lf004b device is programmed on a byte-by- byte basis. before programming, one must ensure that the byte that is being programmed is fully erased. the byte- program operation is initiated by executing a four-byte com- mand load sequence for softwa re data protection with address (pa) and data in the last bus cycle. during the byte-program operation, the row address (a 10 -a 0 ) is latched on the falling edge of r/c# and the column address (a 21 -a 11 ) is latched on the rising edge of r/c#. the data bus is latched on the rising edge of we#. the program operation, once initia ted, will be completed, within 20 s. see figure 15 for timing waveforms. during the pro- gram operation, the only valid reads are data# polling and toggle bit. during the internal program operation, the host is free to perform additional tasks. any commands written during the internal program operation will be ignored. sector-erase operation the sector-erase operation allows the system to erase the device on a sector-by-sector basis. the sector architecture is based on uniform sector size of 4 kbyte. the sector- erase operation is initiated by executing a six-byte com- mand load sequence for softwa re data protection with sector-erase command (30h) and sector address (sa) in the last bus cycle. the internal erase operation begins after the sixth we# pulse. the end-of-erase can be determined using either data# polling or toggle bit methods. see fig- ure 16 for sector-erase timing waveforms. any commands written during the sector-era se operation will be ignored. block-erase operation the block-erase operation allows the system to erase the device in any of the 8 uniform 64 kbyte blocks for the sst49lf004b. the block-erase operation is initiated by executing a six-byte command load sequence for software data protection with block-erase command (50h) and block address (ba) in the last bus cycle. the internal block- erase operation begins after the sixth we# pulse. the end-of-erase can be determined using either data# polling or toggle bit methods. see figure 17 for timing waveforms. any commands written during the block- erase operation will be ignored. chip-erase operation the sst49lf004b device provides a chip-erase opera- tion only in pp mode, which allows the user to erase the entire memory array to the '1's state. this is useful when the entire device must be quickly erased. the chip-erase operation is initiated by executing a six- byte software data protection command sequence with chip-erase command (10h) with address 5555h in the last bus cycle. the internal erase operation begins with the ris- ing edge of the sixth we#. during the internal erase opera- tion, the only valid reads ar e toggle bit or data# polling. see table 10 for the command sequence, figure 18 for timing diagram. any commands written during the chip- erase operation will be ignored. write operation status detection the sst49lf004b device provides two software means to detect the completion of a write (program or erase) cycle, in order to optimize the system write cycle time. the soft- ware detection includes two status bits: data# polling dq 7 and toggle bit dq 6. the end-of-write detection mode is enabled after the rising edge of we# which initiates the internal program or erase operation. the actual completion of the nonvolatile write is asynchro- nous with the system; therefore, either a data# polling or toggle bit read may be simultaneous with the completion of the write cycle. if this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either dq 7 or dq 6. in order to prevent spurious rejec- tion, if an erroneous result occurs, the software routine should include a loop to read the accessed location an addi- tional two (2) times. if both reads are valid, the device has completed the write cycle, otherwise the rejection is valid.
18 preliminary specifications 4 mbit firmware hub sst49lf004b ?2006 silicon storage technology, inc. s71307-01-000 1/06 data# polling dq 7 when the sst49lf004b device is in the internal program operation, any attempt to read dq 7 will produce the com- plement of the true data. once the program operation is completed, dq 7 will produce true data. note that even though dq 7 may have valid data immediately following the completion of an internal write operation, the remaining data outputs may still be in valid. valid data will appear on the entire data bus in subs equent successive read cycles after an interval of 1 s. during an internal erase operation, any attempt to read dq 7 will produce a '0'. once the inter- nal erase operation is completed, dq 7 will produce a '1'. data# polling is valid after the rising edge of the fourth we# pulse for the program operation. for sector-erase, block- erase, or chip-erase, the data# polling is valid after the ris- ing edge of the sixth we# pulse. see figure 13 for data# polling timing diagram. proper status will not be given using data# polling if the address is in the invalid range. toggle bit dq 6 during the internal program or erase operation, any con- secutive attempts to read dq 6 will produce alternating '0's and '1's, i.e., toggling between 0 and 1. when the internal program or erase operation is completed, the toggling will stop. the device is then ready for the next operation. the toggle bit is valid after the rising edge of the fourth we# pulse for program operation. for sector-erase, block- erase or chip-erase, the toggle bit is valid after the rising edge of the sixth we# pulse. see figure 14 for toggle bit timing diagram. data protection (pp mode) the sst49lf004b device provides both hardware and software features to protect nonvolatile data from inadvert- ent writes. hardware data protection noise/glitch protection : a we# pulse of less than 5 ns will not initiate a write cycle. v dd power up/down detection : the write operation is inhibited when v dd is less than 1.5v. write inhibit mode : forcing oe# low, we# high will inhibit the write operation. this prevents inadvertent writes during power-up or power-down. software data protection (sdp) the sst49lf004b provides the jedec approved soft- ware data protection scheme for all data alteration opera- tion, i.e., program and erase. any program operation requires the inclusion of a series of three-byte sequence. the three-byte load sequence is used to initiate the pro- gram operation, providing optimal protection from inadvert- ent write operations, e.g., during the system power-up or power down. any erase operation requires the inclusion of a five-byte load sequence. table 9: o peration m odes s election (pp m ode ) mode rst# oe# we# dq address read v ih v il v ih d out a in program v ih v ih v il d in a in erase v ih v ih v il x 1 sector or block address, xxh for chip-erase reset v il x x high z x write inhibit v ih v il v ih high z/d out x product identification v ih v il v ih manufacturer?s id (bfh) device id 2 a 18 - a 1 = v il , a 0 = v il a 18 - a 1 = v il , a 0 = v ih t9.0 1307 1. x can be v il or v ih , but no other value. 2. device id = 60h for sst49lf004b
preliminary specifications 4 mbit firmware hub sst49lf004b 19 ?2006 silicon storage technology, inc. s71307-01-000 1/06 software comm and sequence table 10: s oftware c ommand s equence command sequence 1st 1 cycle 1. lpc mode use consecutive write cycles to complete a command sequence; pp mode use consecut ive bus cycles to complete a command sequence. 2nd 1 cycle 3rd 1 cycle 4th 1 cycle 5th 1 cycle 6th 1 cycle addr 2 2. yyyy = a[31:16]. in lpc mode, during sdp command sequence, yyyy must be within valid memory address range, see address out of range section for details. in pp mode, yyyy can be v il or v ih , but no other value. data addr 2 data addr 2 data addr 2 data addr 2 data addr 2 data byte-program yyyy 5555h aah yyyy 2aaah 55h yyyy 5555h a0h pa 3 3. pa = program byte address data sector-erase yyyy 5555h aah yyyy 2aaah 55h yyyy 5555h 80h yyyy 5555h aah yyyy 2aaah 55h sa x 4 4. sa x for sector-erase address 30h block-erase yyyy 5555h aah yyyy 2aaah 55h yyyy 5555h 80h yyyy 5555h aah yyyy 2aaah 55h ba x 5 5. ba x for block-erase address 50h chip-erase 6 6. chip-erase is supported in pp mode only yyyy 5555h aah yyyy 2aaah 55h yyyy 5555h 80h yyyy 5555h aah yyyy 2aaah 55h yyyy 5555h 10h software id entry 7,8 7. sst manufacturer?s id = bfh, is read with a 18 -a 0 = 0. with a 18 -a 1 = 0; 49lf004b device id = 60h, is read with a 0 = 1. 8. the device does not remain in software product id mode if powered down. yyyy 5555h aah yyyy 2aaah 55h yyyy 5555h 90h read id software id exit 9 9. both software id exit operations are equivalent xxxx xxxxh f0h software id exit 9 yyyy 5555h aah yyyy 2aaah 55h yyyy 5555h f0h t10.0 1307
20 preliminary specifications 4 mbit firmware hub sst49lf004b ?2006 silicon storage technology, inc. s71307-01-000 1/06 electrical specifications the ac and dc specifications for the lpc interface sign als (la0[3:0], lframe, lclck and rst#) are defined in sec- tion 4.2.2.4 of the pci local bus specification, rev. 2.1. refer to table 11 for the dc voltage and current specifications. refer to tables 16 through 22 for the ac timing specifications for clock, read, write, and reset operations. absolute maximum stress ratings (applied conditions greater than t hose listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater t han those defined in the operational sections of this data sheet is not implied. exposu re to absolute maximum stress rating co nditions may affect device reliability.) temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c d.c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0 .5v to v dd +0.5v transient voltage (<20 ns) on any pin to ground potential 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0v to v dd +2.0v 1. do not violate processor or chip set limitations on the init# pin package power dissipation capability (t a =25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w surface mount solder reflow temperature 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260c for 10 seconds 2. excluding certain with-pb 32-plcc units, all packages are 260 c capable in both non-pb and with-pb solder versions. certain with-pb 32-plcc package types are capable of 240 c for 10 seconds; please consult the factory for the latest information. output short circuit current 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 3. outputs shorted for no more than one second. no more than one output shorted at a time. o perating r ange range ambient temp v dd commercial 0c to +85c 3.0-3.6v ac c onditions of t est 1 1. lpc interface signals use pci load test condition input rise/fall time . . . . . . . . . . . . . . . 3 ns output load . . . . . . . . . . . . . . . . . . . . . c l = 30 pf see figures 21 and 22
preliminary specifications 4 mbit firmware hub sst49lf004b 21 ?2006 silicon storage technology, inc. s71307-01-000 1/06 dc characteristics table 11: dc o perating c haracteristics (a ll i nterfaces ) symbol parameter limits test conditions min max units i dd 1 1. i dd active while a read or write (program or erase) operation is in progress. active v dd current lclk (lpc mode) and address input (pp mode) =v ilt /v iht at f=33 mhz ( lpc mode ) or 1/ trc min ( pp mode ) all other inputs=v il or v ih read 12 ma all outputs = open, v dd =v dd max write 2 2. for pp mode: oe# = we# = v ih ; for lpc mode: f = 1/t rc min, lframe# = v ih . 30 ma see note 2 i sb standby v dd current (lpc interface) 100 a lclk (lpc mode) and address input (pp mode) =v ilt /v iht at f=33 mhz ( lpc mode ) or 1/ trc min ( pp mode ) lframe#=0.9 v dd , f=33 mhz, ce#=0.9 v dd , v dd =v dd max, all other inputs 0.9 v dd or 0.1 v dd i ry 3 3. the device is in ready mode w hen no activity is on the lpc bus. input current for mode and id[3:0] pins 10 ma lclk (lpc mode) and address input (pp mode) =v ilt /v iht at f=33 mhz ( lpc mode ) or 1/ trc min ( pp mode ) lframe#=v il , f=33 mhz, v dd =v dd max all other inputs 0.9 v dd or 0.1 v dd i i input leakage current for mode and id[3:0] pins 200 a v in =gnd to v dd , v dd =v dd max i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 1 a v out =gnd to v dd , v dd =v dd max v ihi init# input high voltage 1.1 v dd +0.5 v v dd =v dd max v ili init# input low voltage -0.5 0.4 v v dd =v dd min v il input low voltage -0.5 0.3 v dd vv dd =v dd min v ih input high voltage 0.5 v dd v dd +0.5 v v dd =v dd max v ol output low voltage 0.1 v dd v v oh output high voltage 0.9 v dd v t11.0 1307 table 12: r ecommended s ystem p ower - up t imings symbol parameter minimum units t pu-read 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er power-up to read operation 100 s t pu-write 1 power-up to write operation 100 s t12.0 1307 table 13: p in c apacitance (v dd =3.3v, t a =25 c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. i/o pin capacitance v i/o =0v 12 pf c in 1 input capacitance v in =0v 12 pf t13.0 1307
22 preliminary specifications 4 mbit firmware hub sst49lf004b ?2006 silicon storage technology, inc. s71307-01-000 1/06 figure 6: lclk w aveform (lpc m ode ) table 14: r eliability c haracteristics symbol parameter minimum spec ification units test method n end 1 endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 + i dd ma jedec standard 78 t14.0 1307 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. table 15: c lock t iming p arameters (lpc m ode ) symbol parameter min max units t cyc lclk cycle time 30 ns t high lclk high time 11 ns t low lclk low time 11 ns - lclk slew rate (peak-to-peak) 1 4 v/ns - rst# or init# slew rate 50 mv/ns t15.0 1307 1307 f05.0 0.4 v dd p-to-p (minimum) t cyc t high t low 0.4 v dd 0.3 v dd 0.6 v dd 0.2 v dd 0.5 v dd
preliminary specifications 4 mbit firmware hub sst49lf004b 23 ?2006 silicon storage technology, inc. s71307-01-000 1/06 ac characteristics (lpc mode) table 16: r ead /w rite c ycle t iming p arameters , v dd =3.0-3.6v (lpc m ode ) symbol parameter min max units t cyc clock cycle time 30 ns t su data set up time to clock rising 7 ns t dh clock rising to data hold time 0 ns t val 1 1. minimum and maximum times have different loads. see pci spec clock rising to data valid 2 11 ns t bp byte programming time 20 s t se sector-erase time 25 ms t be block-erase time 25 ms t on clock rising to active (float to active delay) 2 ns t off clock rising to inactive (active to float delay) 28 ns t16.0 1307 table 17: ac i nput /o utput s pecifications (lpc m ode ) symbol parameter min max units conditions i oh (ac) switching current high -12 v dd -17.1(v dd -v out ) equation c 1 1. see pci spec. ma ma 0 < v out 0.3v dd 0.3v dd < v out < 0.9v dd 0.7v dd < v out < v dd (test point) -32 v dd ma v out = 0.7v dd i ol (ac) switching current low 16 v dd 26.7 v out equation d 1 ma ma v dd >v out 0.6v dd 0.6v dd > v out > 0.1v dd 0.18v dd > v out > 0 (test point) 38 v dd ma v out = 0.18v dd i cl low clamp current -25+(v in +1)/0.015 ma -3 < v in -1 i ch high clamp current 25+(v in -v dd -1)/0.015 ma v dd +4 > v in v dd +1 slewr output rise slew rate 1 4 v/ns 0.2v dd -0.6v dd load slewf output fall slew rate 1 4 v/ns 0.6v dd -0.2v dd load t17.0 1307
24 preliminary specifications 4 mbit firmware hub sst49lf004b ?2006 silicon storage technology, inc. s71307-01-000 1/06 figure 7: o utput t iming p arameters (lpc m ode ) figure 8: i nput t iming p arameters (lpc m ode ) t val t off t on 1307 f06.0 lclk lad [3:0] (valid output data) lad [3:0] (float output data) v test v tl v th t su t dh inputs valid 1307 f07.0 lclk lad [3:0] (valid input data) v test v tl v max v th
preliminary specifications 4 mbit firmware hub sst49lf004b 25 ?2006 silicon storage technology, inc. s71307-01-000 1/06 figure 9: r eset t iming d iagram (lpc m ode ) table 18: i nterface m easurement c ondition p arameters (lpc m ode ) symbol value units v th 1 0.6 v dd v v tl 1 0.2 v dd v v test 0.4 v dd v v max 1 0.4 v dd v input signal edge rate 1 v/ns t18.0 1307 1. the input test environment is done with 0.1 v dd of overdrive over v ih and v il . timing parameters must be met with no more over- drive than this. v max specifies the maximum peak-to-peak waveform allowed for measuring input timing. production testing may use different voltage values, but must correlate results back to these parameters. table 19: r eset t iming p arameters , v dd =3.0-3.6v (lpc m ode ) symbol parameter min max units t prst v dd stable to reset high 100 s t rstp rst# pulse width 100 ns t rstf rst# low to output float 48 ns t rst 1 1. there will be a latency due to t rste if a reset procedure is performed during a program or erase operation, rst# high to lframe# low 5 lclk cycles t rste rst# low to reset during sector-/block-erase or program 10 s t19.0 1307 v dd rst#/init# lframe# lad[3:0] 1307 f08.0 t prst t rstp t rstf t rste sector-/block-erase or program operation aborted t rst
26 preliminary specifications 4 mbit firmware hub sst49lf004b ?2006 silicon storage technology, inc. s71307-01-000 1/06 figure 10: r eset t iming d iagram (pp m ode ) table 20: r eset t iming p arameters , v dd =3.0-3.6v (pp m ode ) symbol parameter min max units t prst v dd stable to reset low 1 ms t rstp rst# pulse width 100 ns t rstf rst# low to output float 48 ns t rst 1 rst# high to row address setup 1 s t rste rst# low to reset during sector-/block-erase or program 10 s t rstc rst# low to reset during chip-erase 50 s t20.0 1307 1. there will be a reset latency of t rste or t rstc if a reset procedure is performed duri ng a programming or erase operational. v dd rst# addresses r/c# dq 7-0 1307 f09.0 t prst t rstp t rstf t rste row address sector-/block-erase or program operation aborted t rst t rstc chip-erase aborted
preliminary specifications 4 mbit firmware hub sst49lf004b 27 ?2006 silicon storage technology, inc. s71307-01-000 1/06 ac characteristics (pp mode) table 21: r ead c ycle t iming p arameters , v dd =3.0-3.6v (pp m ode ) symbol parameter min max units t rc read cycle time 270 ns t rst rst# high to row address setup 1 s t as r/c# address set-up time 45 ns t ah r/c# address hold time 45 ns t aa address access time 120 ns t oe output enable access time 60 ns t olz oe# low to active output 0 ns t ohz oe# high to high-z output 35 ns t oh output hold from address change 0 ns t21.0 1307 table 22: p rogram /e rase c ycle t iming p arameters , v dd =3.0-3.6v (pp m ode ) symbol parameter min max units t rst rst# high to row address setup 1 s t as r/c# address setup time 45 ns t ah r/c# address hold time 45 ns t cwh r/c# to write enable high time 50 ns t oes oe# high setup time 20 ns t oeh oe# high hold time 20 ns t oep oe# to data# polling delay 60 ns t oet oe# to toggle bit delay 60 ns t wp we# pulse width 100 ns t wph we# pulse width high 100 ns t ds data setup time 50 ns t dh data hold time 5 ns t ida software id access and exit time 150 ns t bp byte programming time 20 s t se sector-erase time 25 ms t be block-erase time 25 ms t sce chip-erase time 100 ms t22.0 1307
28 preliminary specifications 4 mbit firmware hub sst49lf004b ?2006 silicon storage technology, inc. s71307-01-000 1/06 figure 11: r ead c ycle t iming d iagram (pp m ode ) figure 12: w rite c ycle t iming d iagram (pp m ode ) rst# t rst 1307 f10.0 column address data valid high-z row address column address row address addresses r/c# v ih high-z t rc t as t ah t ah t aa t oe t olz t ohz t oh t as we# oe# dq 7-0 1307 f11.0 column address row address data valid rst# addresses r/c# t rst t as t ah t cwh t wp t oes t wph t oeh t dh t ds t ah t as we# oe# dq 7-0
preliminary specifications 4 mbit firmware hub sst49lf004b 29 ?2006 silicon storage technology, inc. s71307-01-000 1/06 figure 13: d ata # p olling t iming d iagram (pp m ode ) figure 14: t oggle b it t iming d iagram (pp m ode ) 1307 f12.0 addresses r/c# t oep row column we# oe# dq 7 d# d d# d 1307 f13.0 addresses r/c# t oet row column we# oe# dq 6 d d
30 preliminary specifications 4 mbit firmware hub sst49lf004b ?2006 silicon storage technology, inc. s71307-01-000 1/06 figure 15: b yte -p rogram t iming d iagram (pp m ode ) figure 16: s ector -e rase t iming d iagram (pp m ode ) 5555 5555 2aaa a 14-0 r/c# oe# we# dq 7-0 ba internal program starts aa 55 a0 data ba = byte-program address 1307 f14.0 5555 5555 5555 2aaa sa x 2aaa a 14-0 r/c# oe# we# dq 7-0 internal erase starts aa 55 80 aa 55 30 sa x = sector address 1307 f15.0
preliminary specifications 4 mbit firmware hub sst49lf004b 31 ?2006 silicon storage technology, inc. s71307-01-000 1/06 figure 17: b lock -e rase t iming d iagram (pp m ode ) figure 18: c hip -e rase t iming d iagram (pp m ode ) 5555 5555 5555 2aaa ba x 2aaa a 14-0 r/c# oe# we# dq 7-0 internal erase starts aa 55 80 aa 55 50 ba x = block address 1307 f16.0 5555 5555 5555 2aaa 5555 2aaa a 14-0 r/c# oe# we# dq 7-0 internal erase starts aa 55 80 aa 55 10 1307 f17.0
32 preliminary specifications 4 mbit firmware hub sst49lf004b ?2006 silicon storage technology, inc. s71307-01-000 1/06 figure 19: s oftware id e ntry and r ead (pp m ode ) figure 20: s oftware id e xit (pp m ode ) 5555 5555 0000 0001 2aaa a 14-0 r/c# oe# we# dq 7-0 aa 1307 f18.0 device id bf 55 90 t wp t wph t ida t aa three-byte sequence for software id entry device id = 60h for sst49lf004b 5555 5555 2aaa a 14-0 r/c# oe# we# dq 7-0 aa 1307 f19.0 55 f0 t ida
preliminary specifications 4 mbit firmware hub sst49lf004b 33 ?2006 silicon storage technology, inc. s71307-01-000 1/06 figure 21: ac i nput /o utput r eference w aveforms figure 22: a t est l oad e xample 1307 f20.0 reference points output input v it v iht v ilt v ot ac test inputs are driven at v iht (0.9 v dd ) for a logic ?1? and v ilt (0.1 v dd ) for a logic ?0?. measurement reference points for inputs and outputs are v it (0.5 v dd ) and v ot (0.5 v dd ). input rise and fall times (10% ? 90%) are <5 ns. note: v it - v input te s t v ot - v output te s t v iht - v input high test v ilt - v input low test 1307 f21.0 to tester to dut c l
34 preliminary specifications 4 mbit firmware hub sst49lf004b ?2006 silicon storage technology, inc. s71307-01-000 1/06 product ordering information valid combinations for sst49lf004b sst49lf004b-33-4c-nhe SST49LF004B-33-4C-WHe note: valid combinations are those products in mass producti on or will be in mass production. consult your sst sales representative to confirm availability of valid combinat ions and to determine availability of new combinations. environmental attribute e 1 = non-pb package modifier h = 32 leads package type n = plcc w = tsop (type 1, die up, 8mm x 14mm) operating temperature c = commercial = 0c to +85c minimum endurance 4 = 10,000 cycles serial access clock frequency 33 = 33 mhz device density 004 = 4 mbit voltage range l = 3.0-3.6v product series 49 = lpc firmware memories 1. environmental suffix ?e? denotes non-pb solder. sst non-pb solder devices are ?rohs compliant?. device speed suffix1 suffix2 sst49 l f004 b- xxx -x x -x x x
preliminary specifications 4 mbit firmware hub sst49lf004b 35 ?2006 silicon storage technology, inc. s71307-01-000 1/06 packaging diagrams 32- lead p lastic l ead c hip c arrier (plcc) sst p ackage c ode : nh .040 .030 .021 .013 .530 .490 .095 .075 .140 .125 .032 .026 .032 .026 .029 .023 .453 .447 .553 .547 .595 .585 .495 .485 .112 .106 .042 .048 .048 .042 .015 min. top view side view bottom view 1 232 .400 bsc 32-plcc-nh-3 note: 1. complies with jedec publication 95 ms-016 ae dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in inches (max/min). 3. dimensions do not include mold flash. maximum allowable mold flash is .008 inches. 4. coplanarity: 4 mils. .050 bsc .050 bsc optional pin #1 identifier .020 r. max. r. x 30
36 preliminary specifications 4 mbit firmware hub sst49lf004b ?2006 silicon storage technology, inc. s71307-01-000 1/06 32- lead t hin s mall o utline p ackage (tsop) 8 mm x 14 mm sst p ackage c ode : wh table 23: r evision h istory number description date 00 ? initial release oct 2005 01 ? updated surface mount solder reflow temperature information ? added nh package information. jan 2005 32-tsop-wh-7 note: 1. complies with jedec publication 95 mo-142 ba dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in millimeters (max/min). 3. coplanarity: 0.1 mm 4. maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 1.20 max. 1mm pin # 1 identifier 12.50 12.30 14.20 13.80 0.70 0.50 8.10 7.90 0.27 0.17 0. 50 bsc 1.05 0.95 0.15 0.05 0.70 0.50 0?- 5? detail silicon storage technology, inc. ? 1171 sonora court ? sunnyvale, ca 94086 ? telephone 408-735-9110 ? fax 408-735-9036 www.superflash.com or www.sst.com

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